(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form shallow trench isolation (STI), regions, for semiconductor devices.
(2) Description of Prior Art
The objective of increasing semiconductor device performance has resulted in the use of shallow trench isolation (STI), regions, replacing field oxide (FOX), regions, for device isolation purposes. Unwanted lateral oxidation, or xe2x80x9cbirds beakxe2x80x9d formation, occurring during the high temperature oxidation procedures used for FOX processing, necessitates the use of larger device dimensions to accommodate the unwanted birds beak or lateral oxide growth, resulting in semiconductor devices with larger then desired device regions. This in turn results in increases in parasitic junction capacitance, deleteriously influencing the performance of semiconductor devices fabricated with FOX isolation regions. The use of STI regions, formed by defining a trench shape in a specific region of the semiconductor substrate, followed by filling of the anisotropically formed shallow trench shape, avoids birds beak formation encountered with isolation regions obtained via FOX processing. Thus STI processing allows smaller devices to be realized, offering less junction capacitance and thus increased device performance when compared to counterparts fabricated using FOX technology.
The use of STI processing however has to be optimized to avoid specific structural problems that can degrade device yield and reliability. The insulator filled STI regions can be comprised of narrow width STI shapes, as well as larger width STI shapes. When filling these various shaped STI regions with chemically vapor deposited (CVD), insulator layers, the topography created by the CVD insulator layer located between densely packed, STI shapes, is higher than the topography created by the same CVD insulator layer located either in a wide STI shape, or from the CVD insulator located in large spaces between STI shapes. A chemical mechanical polishing (CMP), procedure, used to remove unwanted CVD material from regions other than the CVD layer in the STI shapes, can unfortunately xe2x80x9cdishxe2x80x9d or remove CVD layer fill from inside the lower topography regions, such as wide width STI shapes, or from large areas located between STI shapes. In addition to the lack of planarity resulting from the dishing phenomena, the CMP procedure applied to this type of topography can roughen the top surface of the CVD layer filling the STI shapes, again adversely influencing the objective of creating a smooth topography needed for subsequent overlying insulator and conductor structures.
This invention will teach a process of forming insulator filled, STI regions, using a CMP procedure for planarization via removal of unwanted insulator, however avoiding the unwanted xe2x80x9cdishingxe2x80x9d phenomena, and without the unwanted roughening of the surface of the insulator layer located in the STI regions. Prior art, such as Yu et al, in U.S. Pat. No. 6,010,948, describe a process of filling STI regions with a boro-phosphosilicate glass (BPSG), layer, resulting in a smooth topography of insulator in all dimensioned STI regions as a result of reflowing of the BPSG layer. The present invention however will describe a procedure in which reflowed BPSG is used only as a disposable layer, allowing a smooth topography of silicon oxide, in the STI shapes, to be realized via a CMP procedure removing the entire planarizing BPSG layer, and a portion of the underlying silicon oxide layer, resulting in a smooth top surface topography for silicon oxide filled, STI regions.
It is an object of this invention to form insulator filled, STI regions, in a semiconductor substrate.
It is another object of this invention to form the STI shapes via anisotropic, reactive ion etching (RIE), procedures, then fill the STI shapes with an underlying silicon oxide layer, and with an overlying BPSG layer.
It is yet another object of this invention to fill the STI shapes with an underlying silicon oxide layer, and an overlying spin on glass (SOG), layer.
It is still another object of this invention to perform an anneal procedure to reflow the blanket BPSG layer, creating a smooth top surface topography for the BPSG layer, overlying the silicon oxide filled STI regions.
It is still yet another object of this invention to perform a CMP procedure to completely remove the reflowed BPSG layer, and a portion of the underlying silicon oxide layer, resulting in a smooth top surface topography for the silicon oxide filled, STI regions.
In accordance with the present invention a method of forming insulator filled STI regions, for a semiconductor device, featuring a disposable, reflowed BPSG layer, used to allow a smooth top surface topography of the insulator filled STI regions, to be formed via a CMP procedure, is described. After growth or deposition of an underlying silicon oxide layer, and deposition of an overlying silicon nitride layer, on a semiconductor, photolithographic and anisotropic RIE procedures are employed to define openings in the silicon nitride and silicon oxide layer, and to form the STI shapes in the semiconductor substrate. A thermally grown silicon dioxide layer is then formed, lining the exposed surfaces of the STI shapes, followed by the deposition of a high density plasma, (HDP), deposition of silicon oxide, completely filling the STI shapes, as well as overlying the top surface of the silicon nitride layer, located between STI shapes. A BPSG layer is next deposited on the top surface of the HDP silicon oxide layer, filling the spaces created by the underlying silicon oxide layer in the STI shapes, and the silicon oxide layer located on the silicon nitride layer. An anneal procedure is then used to reflow the BPSG layer resulting in a BPSG layer exhibiting a smooth top surface topography. A CMP procedure is next used to completely remove the reflowed BPSG layer, and a portion of the underlying HDP silicon oxide layer, with the CMP procedure terminating at the top surface of the silicon nitride layer, resulting in silicon oxide filled, STI regions. After removal of the silicon nitride layer, and of the silicon oxide layer, semiconductor devices are formed on regions of the semiconductor substrate located between the silicon oxide filled, STI regions.
A second embodiment of this invention is the use of a SOG layer, replacing the BPSG layer, for planarization purposes, while a third embodiment entails removal of reflowed BPSG and a portion of the underlying HDP silicon oxide layer, from regions prone to the xe2x80x9cdishingxe2x80x9d phenomena, prior to the CMP procedure, via photolithographic and dry etching procedures.